Using Circuit Simulators to Sensitivity-Factor Analysis in Analog Circuits

In this paper, a procedure to calculate the sensitivity factors of the quiescent drain current of a field-effect transistor operating in the active region is presented. This one can be applied in conjunction with a general-purpose circuit simulator for bias circuits with bipolar junction transistors or field-effect transistors. We showed that the sensitivity factors of the quiescent drain current can be calculated by repeated simulations of the bias circuit modified according to the change of a parameter value. How to apply the proposed procedure is illustrated on the two common bias circuits for which comparatively studies are performed. Such a procedure based on a circuit simulator allows the students to verify and, if necessary, modify the bias circuit design on desired direction and rapidly test it. Key-Words: Sensitivity factor analysis, Bias circuits, FET.